1) Field of the Invention
This invention relates generally to fabrication of a semiconductor device and more particularly to a method for planarizing metal contacts for local interconnects.
2) Description of the Prior Art
As the physical geometry of semiconductor devices continues to shrink, metal damascene processes play an important role in forming contacts for local interconnects. In a typical metal damascene process, a dielectric layer (eg ILD) is formed over a semiconductor structure and one more devices. The dielectric layer is patterned to form contact openings. A barrier layer is deposited over the semiconductor structure, and a contact layer, composed of a metal such as tungsten, is deposited on the barrier layer. The contact layer and the barrier layer are planarized using a chemical mechanical polishing process (CMP).
However, the typical metal damascene process has several problems. Because the metal CMP is highly selective to the contact layer, more metal is removed in the middle of the contact than at the edges near the dielectric layer. This condition, which is known as dishing, can cause poor planarity and lead to higher contact resistance. Insufficient chemical mechanical polishing can leave metal residue causing shorting between interconnect lines. Excess chemical mechanical polishing can cause erosion of the dielectric layer, reducing the step height of the dielectric layer.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,837,612 (Ajuria et al.) shows a method for forming a shallow trench isolation (STI) with reduced erosion by forming polysilicon oxide layers on the sidewalls and top corners of an STI structure. Since the polysilicon oxide layers have a slower etch rate than TEOS oxide, which forms the bulk of the STI structure, STI erosion is reduced.
U.S. Pat. No. 5,910,022 (Weling) and U.S. Pat. No. 5,726,099 (Jasco) show chemical mechanical polishing processes which remove metal over a dielectric layer and simultaneously planarize the dielectric layer by using a slurry which provides approximately equal selectivity of metal and dielectric.
U.S. Pat. No. 5,916,855 (Avanzino et al.) shows a tungsten and titanium nitride chemical mechanical polishing process.
U.S. Pat. No. 5,578,523 (Fiodalice et al.) shows a dual damascene chemical mechanical polishing process.
U.S. Pat. No. 5,858,813 (Scherber et al.) teaches a chemical mechanical polishing slurry with high selectivity of metal to silicon dioxide.
U.S. Pat. No. 5,804,084 (Nasby et al.) shows a chemical mechanical polishing process for planarizing sacrificial oxide layers in a micromachining process.